Evolution of computer architecture · CPUs, parallel systems and alternative machines

An extensive, selectively curated history of computer architecture, from mechanical and analog designs through stored-program machines, CPU families, parallel computers, dedicated language hardware and quantum experiments. Gregorian calendar, UTC. Research cutoff: 3 November 2026. This is a map of major design directions and tradeoffs, not an inventory of every processor or a claim to include every advance.

How to explore

Use Separate by tags to compare strands: stored program, von Neumann, Harvard architecture, microarchitecture, instruction sets, RISC, x86, Arm, stack machines, Lisp machines, dataflow, VLIW, EPIC, superscalar, out of order, SIMD, MIMD, shared memory, distributed memory, clusters, neuromorphic, quantum, security and chiplets. Milestones can carry several tags because these properties often coexist. Expand a moment for its sources, date evidence, linked comparisons and attached concept notes.

The full view includes nineteenth-century design work. Zoom into 1940–2026 for the denser electronic-computing history. Fifteen reading bands provide editorial navigation; their endpoints are not whole-paradigm birth/death dates or support windows. Concept cards are undated explanations attached to genuine milestones.

Architecture has several levels

An instruction-set architecture defines a software-visible machine interface. A microarchitecture implements it with a particular pipeline, scheduler, execution units and memory hierarchy. A system architecture combines processors, memory, I/O and interconnect. A fabrication process, package arrangement and programming API form additional layers. The timeline dates them separately.

A modern processor may simultaneously be Arm or x86, superscalar, speculative, out of order, SIMD-capable, multicore and heterogeneous. These are not rival names for one classification. Flynn’s instruction/data-stream taxonomy is useful at a chosen level; SISD, SIMD, MISD and MIMD do not replace descriptions of cache coherence, topology or scheduling. SPMD is a programming pattern. SIMD lanes, SMT contexts and physical cores are different resources.

Routes through the history

The companion GPU/ASIC programming history goes further into programming interfaces and dated applications. Dynamically typed functional programming covers the Lisp software and teaching traditions. This architecture survey references those connections while keeping its focus on machines, interfaces and organization.

Commercial retreat and surviving ideas

Orange/brown experimental and retreat markers help compare designs that did not become a permanent mainstream product family. Setun demonstrates a real ternary machine, not proof of general ternary superiority. Stretch misses its ambition while contributing later engineering experience. Dedicated Lisp hardware loses its market position while Lisp, runtime techniques and interactive development continue. Thinking Machines’ company failure is not the end of parallel computing. Crusoe explores binary translation onto VLIW. Itanium’s exit does not end compiler scheduling or all VLIW-derived designs. AMULET and dataflow prototypes are evaluated as research systems rather than dismissed merely for not replacing every desktop CPU.

“Survival” here describes documented continuation or a conceptual comparison. Similarity alone does not establish a circuit lineage, code fork or a single cause for commercial failure. Only specifically documented continuations receive directional arrowheads. Other relationship arcs are labeled reading paths or comparisons, with their evidence in the moment details; a path is not an ancestry claim.

Quantum claims are kept specific

Proposals, algorithms, controlled experiments, cloud access and error-correction results are different milestones. A physical-qubit total does not rank every platform’s useful power. Annealers, analog simulators, photonic samplers and universal gate models are not interchangeable. The Sycamore and Jiuzhang entries concern defined sampling tasks and changing classical comparisons, rather than universal application speedups.

The December 2024 Willow-related publication demonstrates below-threshold logical memory; its journal volume is dated 2025. Logical memory is distinct from a complete scalable fault-tolerant application computer. Neutral-atom logical experiments, trapped-ion proposals and Ocelot’s bosonic error-management architecture retain their respective experimental conditions. Shor’s theoretical factoring result and the later small NMR experiment are separate; neither is portrayed as the demonstrated ability to break modern cryptographic keys.

Dates and evidence

Sources prioritize original papers, manuals, creator accounts, manufacturer announcements, standards bodies, university project archives and institutional artifact records. Publisher-registered bibliographic metadata checks paper identity where older publishers restrict automated access. Museum histories and contemporary technical reporting supply selected contextual dates. Each moment records whether it is a proposal, publication, prototype, commercial launch, operational installation, benchmark, retrospective or snapshot.

Year-only dates plot at January 1; month-only dates plot on their first day. These anchors do not claim exact days. Coarse dates have presumptive outlines, and UTC midnight is not an inferred historical clock time. Announcement, shipment and operation may differ: ILLIAC IV delivery precedes operational declaration; CADR’s 1978 photographic record precedes its 1979 memo; ASCI Red’s 1996 teraflop demonstration precedes full operation in June 1997. Itanium’s 2001 readiness announcement precedes expected system shipments, while its 2019 exit notice specifies later order/shipment deadlines.

The conventional von Neumann name identifies an influential stored-program organization; it is not used to erase the collaborative EDVAC-era work. Harvard terminology is explained as an organization of instruction/data access, with modern split-cache designs kept distinct from the 1944 Mark I. Historical models and product names are not silently treated as compatible ISAs.

Media

Seven individually credited Commons images use public-domain or Creative Commons licenses allowing reuse. Dates of museum photographs and later hardware illustrations are separate from the milestones. The FPGA photograph shows XC2018 rather than the first XC2064; the later Quantum System One is not the 2016 cloud processor. Image availability does not transfer rights to entire manuals or journal articles. No changes beyond thumbnail scaling.

• USGov-Military-Army · Eniac Aberdeen.jpg · Public domain; rights.
• Myra Siason · IBM System 360 Model 40 with open gates.jpg · CC BY-SA 2.0; rights.
• OJB Quantum · IBM Quantum System One.jpg · CC BY 4.0; rights.
• NecroBones at English Wikipedia · Cray-1 (1).jpg.jpg) · Public domain; rights.
• NASA Ames Research Center / Lee Jones · ILLIAC IV Quadrant with processing unit extended (ARC-1972-A72-4297).jpg.jpg) · Public domain; rights.
• Swtpc6800 Michael Holley · Xilinx XC2018 LCA.jpg · CC0; [rights](http://creativecommons.org/publicdomain/zero/1.0/deed.en).
• Daderot · CADR - The Lisp Machine, late 1970s, view 3 - MIT Museum - DSC03754.JPG · CC0; [rights](http://creativecommons.org/publicdomain/zero/1.0/deed.en).

Duration correction: Ongoing subjects previously drawn through a present/research cutoff are represented at their original starts, with no end asserted. Existing moments at those coordinates are reused; their attached cards retain the former duration’s notes, sources, tags and media. Bounded historical and coverage intervals remain durations.